White Paper: International Test Solutions
Technological demands for 5G connectivity, Internet of Things (IoT), artificial intelligence (AI), wearables, and automobiles (self-driving, electrified, etc.) are key drivers behind the next technology nodes. In today’s commercial landscape, there are extremely high costs associated with the fab investment for the process development. As a result, only a few IDM (integrated device manufacturers) and foundries, such as Intel, Samsung, and TSMC, are actively pursuing Moore’s Law for monolithic silicon wafer scaling.
To attain these faster and denser integrated circuits, photolithography has relied on (1) progressively reducing the exposure wavelengths whereby the most advanced nodes are now utilizing Extreme Ultraviolet (EUV) Lithography; and (2) increasing the numerical aperture whereby advanced immersion systems are being implemented. In both fabrication techniques, the depth of focus is absolutely critical, and the entire surface of a clamped wafer substrate must have minimal non-planarity to fall within an extremely tight depth of focus.
To maintain the necessary depth of focus, all the critical surfaces within the manufacturing tool chamber must be totally co-planar. For the wafer itself, non-planarity can come from variations in warp, bow, and thickness of the substrate. In each case, the required geometrical properties of the wafer can be attained through various precision polishing processes. Within the tool, a chuck (or table) provides an extremely flat reference surface onto which the wafer will be clamped using vacuum or electrostatic force. A high degree surface flatness of the chuck can be attained through high precision lapping and polish processes. Finally, to assure flatness after clamping, the chucking method and force are optimized based on the wafer substrate material as well as the chuck design. Supply management of substrate material and hardware service steps can be performed to comprehensively address non-planarity issues as part of a regularly scheduled maintenance.
Particle contamination is an unpredictable and, arguably, a significant problem for creating critical non-planarity issues during the fabrication process. Of greatest concern is a particle trapped between the backside wafer and wafer chuck surface. The particle contaminant could be crushed or at worst embedded into the wafer or wafer chuck. As a result, there could occur a critical backside leak fault or an out-of-plane distortion (i.e., a “hot-spot”). Unscheduled downtime to properly wet clean the chambers can have dramatic effects on tool and chamber availability, thereby affecting wafer throughput.